Impact of Technology Scaling on Bridging Fault Modeling and Detection in CMOS Circuits

ii I hereby declare that I am the sole author of this thesis. I authorize the University of Waterloo to lend this thesis to other institutions or individuals for the purpose of scholarly research. I authorize the University of Waterloo to reproduce this thesis by photocoping or other means, in total or in part, at the request of other institutions or individuals for the purpose of scholarly research. The University of Waterloo requires the signatures of all persons using or photocopying this thesis. Please sign below, and give address and data. iv Acknowledgements I wish to express my extreme gratitude to my supervisor, Dr. M. Sachdev, for his guidance and support throughout my university career, especially during my graduate research, and helpful advice during the writing of this thesis. I also wish to thank Dr. Michael S. Obrecht for many useful comments and conversations regarding my research, and my thesis readers for their helpful comments and constructive critiques. I would like to thank the members of the VLSI Research Group at the University of Waterloo for their assistance. v Dedication This thesis is dedicated to my mother and wife, and in memory of my father, who began my education in microelectronics area and who motivated me to continue it. Abstract CMOS technology scaling allowed to reduce MOSFET dimensions from 10 µm in the 1970's to a present day size of 0.13 µm. The ability to improve performance consistently with decreasing power consumption has made CMOS technology the dominant technology for integrated circuits. The scaling of the MOS transistor has been the primary factor driving improvement in microprocessor performance. However, recent developments and future trends in CMOS process and design technologies are introducing new levels of complexity in testing. For example, the consequent reduction of MOSFET threshold voltage and the increase of leakage current are decreasing the effectiveness of quiescent current testing (I ddq) because the reduced ratio between the MOSFET "on" and "off" currents is making this testing technique impracticable for deep submicron technologies. In this thesis we investigate the behavior of bridging faults (BF) in CMOS digital integrated circuits and analyze the impact of BFs on logic margin and logic swing of sequential and combinational CMOS circuits under different operating conditions and technology feature sizes. The BF model in CMOS digital circuits was developed. This model explains the impact of technology scaling on effectiveness of BF detection using logic …